FIG. 1 is a schematic representation of a typical memory device 10. The memory device 10 comprises an array of cells 5AA, 5BB, 5BA, etc. Each cell is used to store one bit of data. Each row of cells in the array is linked by a word line 8A, 8B, etc, while each column of cells in the array is linked by a bit line, 12A, 12B, 12C, etc. Any given cell can therefore be uniquely specified by a combination of the appropriate word line 8 and bit line 12. For example, as shown in FIG. 1, cell 5EF can be accessed by the combination of word line 8E and bit line 12F. An X-decoder 35 (also referred to as a row decoder) is used to select a word line 8, while a Y-decoder 25 (also referred to as a column decoder) is used to select a bit line 12, both dependent upon the specified address of a memory operation.
The memory device 10 further includes a sense amplifier 20 connected to each bit line. The sense amplifier is used to read data from or write data to a desired memory cell 5 in accordance with the selected word line 8 and bit line 12. Note that although sense amplifier 20 is shown in FIG. 1 as a single block, it is usually implemented as a separate sense amplifier per bit line.
The memory device 10 of FIG. 1 comprises an 8×8 cell storage array, but it will be appreciated that most commercial memory devices incorporate a much larger number of cells. In addition, the number of rows of cells in the array will often be different from the number of columns. Note that some memory devices may comprise multiple cell storage arrays. One example of a known memory device is described in U.S. Pat. No. 5,463,586.
The implementation of an individual memory cell 5 within memory device 10 depends upon the particular type of memory device. Where memory device 10 represents non-volatile ROM (NVROM), such as flash memory, each cell 5 may comprise a floating gate which is used to control the threshold voltage of a cell transistor. The value stored in the cell depends upon the setting of the floating gate. If the floating gate is put into a charged or programmed state, this raises the threshold voltage. Alternatively, if the floating gate is returned to its unprogrammed state by an erasure process, this lowers the threshold voltage. (Note that some other types of non-volatile memory do not have a floating gate).
A non-volatile memory cell may be programmed or erased by applying appropriate voltages to the cell transistor. For example, in one type of flash memory, a cell may be programmed by applying a predetermined raised voltage to the gate and drain of the cell transistor, while in a read operation, a lower predetermined voltage is applied to the gate and drain of the cell transistor. The lower predetermined voltage is intermediate the threshold voltage for the programmed and non-programmed states. As a result, the programmed cells do not conduct (or conduct poorly), and so are taken as having binary value 0, while the non-programmed (and erased) cells conduct well, and so are taken as having binary value 1.
Flash memory devices are usually provided with one or more reference cells. For example, a flash memory may contain a read (RD) reference cell which is used in a comparison as part of the read operation to determine whether a given cell is programmed (binary value 0) or not programmed (binary value 1). The comparison may be implemented by sense amplifier 20 in the form of a comparator or differential amplifier, which is used to detect whether the current (or voltage) from the read reference cell is greater or less than the current (or voltage) from the storage cell on the word and bit line being read.
This situation is illustrated in FIG. 2, which shows a plot of integrated current through the sense amplifier against time. FIG. 2 shows three different lines, one labelled A representing a programmed cell, another labelled C representing an erased (or non-programmed) cell, and another labelled B representing the read reference cell. It will be seen that the output current for the read reference cell is intermediate the output currents for the programmed cell and the erased cell.
The discrimination between a programmed cell and an erased cell is made at time T=T1. In FIG. 2, the integrated current from the erased cell at time T1 is denoted C1, the integrated current from the reference cell at time T1 is denoted B1, and the integrated current from the programmed cell at time T1 is denoted A1, where C1>B1>A1. Accordingly, if a memory cell is read at time T1, it is regarded as programmed (i.e. a binary 0) if the integrated current is less than B1, and erased (i.e. a binary 1) if the integrated current is greater than B1.
Another example of a reference cell is an erase-verify (EV) reference cell, which is used during erase operations to confirm that each memory cell 5 has been successfully erased. In one implementation, following erasure, it is confirmed that the threshold voltage for each of the erased memory cells 5 is less than the threshold voltage for the EV reference cell. This ensures that the memory cells will henceforth conduct during a read operation, and therefore be taken as a storing a binary value 1—i.e. the memory cells have been properly erased. It will be appreciated that the EV reference cell may also be used for a comparison of current (such as shown in FIG. 2), rather than a direct comparison of threshold voltage.
Similarly, a program-verify (PV) reference cell may be utilised during program operations to confirm that each memory cell 5 has been successfully programmed. In particular, following programming, it is confirmed that the threshold voltage for each of the programmed memory cells 5 is greater than the threshold voltage for the PV cell. This ensures that the memory cells will henceforth not conduct during a read operation, and therefore be taken as storing a binary value 0—i.e. the memory cells have been properly programmed. Again, the PV reference cell may also be used for a comparison of current (such as shown in FIG. 2), rather than a direct comparison of threshold voltage.
Note that the threshold voltage of the read reference cell is normally greater than the threshold voltage of the erase-verify reference cell, and lower than the threshold voltage of the program-verify reference cell. Conversely, the current through a read reference cell is normally lower than the current through the erase-verify reference cell, and greater than the current through the program-verify reference cell.
An important consideration in designing flash memory is to set the appropriate threshold voltage for the read reference cell, the erase-verify reference cell, and the program verify reference cell. The settings of these reference cells must be able to accommodate manufacturing and other variations in the storage cells 5 of the device. It is sometimes possible during set-up of a device to adjust the threshold voltage of the storage cells 5 to conform to the reference cells, but this can be time-consuming. U.S. Pat. No. 6,449,190 describes a flash memory device in which the threshold voltages of the reference cells are adapted to match the storage cells of a given device.
U.S. Pat. No. 6,421,275 describes a method for adjusting a (read) reference current of a flash nitride ROM (NROM), which uses an oxide-nitride-oxide layer for charge storage (rather than a floating gate). In particular, the reference current is compared against an adjusting current in order to modify the reference current to an appropriate value.
U.S. Pat. No. 6,459,620 describes sense amplifier offset cancellation in non-volatile memory circuits by the use of dedicated programmed reference non-volatile memory cells. In particular, the comparison between a reference cell and a storage cell being read can be impacted by variations or offset in the comparator or sense amplifier for the bit line to which the storage cell being read is attached. Accordingly, a dedicated reference cell may be associated with each comparator. The dedicated reference cell can then be programmed to compensate for any internal offset within the comparator. This is achieved by examining the output from the comparator based on providing the reference cell output to the comparator in conjunction with a programmed predetermined threshold voltage.
Nevertheless, existing approaches do not fully accommodate all variations within a flash memory when setting reference cell levels.